1. Field of the Invention
The invention relates to the generation of interrupts in a computer system, and more particularly, to the mapping or redirection of interrupts generated on a first bus to interrupts defined by a second bus.
2. Description of the Related Art
When International Business Machines (IBM) first introduced its personal computers, the bus architecture standard used in those computers was the original IBM PC system architecture. As memory and peripheral devices increased in size and speed, the timing standard and data width used in the original IBM PC architecture was too slow and too narrow to take advantage of the advances in memory and peripheral speeds. As a result, IBM developed the PC/AT to allow the faster memory devices to be utilized more effectively. The architecture of the PC/AT has become known as the Industry Standard Architecture (ISA). However, as computer system components grew ever more powerful, ISA proved to be inadequate, which necessitated the development of a new bus standard, known as the Extended Industry Standard Architecture (EISA), to take advantage of the extra options and features available from the system components.
In computer systems, peripheral or I/O devices, such as keyboards, hard disk drives, floppy disk drives, display monitors and other components, require servicing by the microprocessor from time to time. One method of determining whether the devices require servicing by the microprocessor is by use of polling, in which the microprocessor tests each I/O device in sequence to determine if the device needs servicing. A disadvantage of this method is that the microprocessor is continuously executing polling cycles. Thus, an increase in the number of I/O devices would adversely affect the system throughput.
In response to the limitations of the polled method of determining whether I/O devices require servicing, a method known as interrupt driven I/O was developed. In the interrupt method, each I/O device asserts an interrupt signal whenever it requires servicing by the microprocessor. In computer systems incorporating interrupt driven I/O, a programmable interrupt controller (PIC) is coupled to the system bus to function as an overall manager in accepting interrupt requests from the I/O devices. The PIC determines which of the incoming requests has the highest priority and ascertains whether any of the incoming requests has a higher priority value then the level currently being serviced. The PIC issues an interrupt to the microprocessor based on this determination. Thus, the interrupt method allows an I/O device to provide an external asynchronous input that informs the microprocessor when servicing is required. As a result, the microprocessor is freed from having to perform unnecessary polling cycles on the system bus to determine when servicing is required by the I/O devices.
In ISA and EISA systems, the interrupt controller includes two 8259 programmable interrupt controllers by Intel Corporation (Intel). Each 8259 interrupt controller handles up to eight vectored priority interrupts for the microprocessor. One of the two 8259 interrupt controllers is classified as the master interrupt controller, which receives EISA interrupt request lines EISA.sub.-- IRQ&lt;7:0&gt;. The other interrupt controller is classified as the slave interrupt controller, which receives interrupt request lines EISA.sub.-- IRQ&lt;15:8&gt;. Each 8259 interrupt controller has an interrupt output INT. When one or more of the interrupt request lines EISA.sub.-- IRQ&lt;15:0&gt;are asserted, the 8259 interrupt controllers make a determination of the priority of the EISA.sub.-- IRQ lines that are asserted and whether any of the EISA.sub.-- IRQ lines are to be masked. If a mask bit corresponding to an EISA.sub.-- IRQ line is set, then the 8259 interrupt controller ignores the assertion of the EISA.sub.-- IRQ line. The EISA interrupts have the following priority arrangement from the highest priority to the lowest: EISA.sub.-- IRQ0, EISA.sub.-- IRQ1, EISA.sub.-- IRQ8, EISA.sub.-- IRQ9, EISA.sub.-- IRQ10, EISA.sub.-- IRQll, EISA.sub.-- IRQ12, EISA.sub.-- IRQ13, EISA.sub.-- IRQ14, EISA.sub.-- IRQ15, EISA.sub.-- IRQ3, EISA.sub.-- IRQ4, EISA.sub.-- IRQ5, EISA.sub.-- IRQ6 and EISA.sub.-- IRQ7. After the 8259 interrupt controllers have completed their determinations, the master interrupt controller asserts its interrupt output to the system bus. When the microprocessor receives an interrupt request, it finishes completion of the current instruction. Next, the microprocessor saves the state of the interrupted program, which includes its address and the contents of certain registers, onto a stack to allow resumption of the interrupted program once the interrupt has been serviced. Then the microprocessor executes an interrupt acknowledge cycle, which causes a signal INTA, to be generated on the EISA system bus. When the 8259 interrupt controllers receive the signal INTA, indicating an interrupt acknowledge cycle, one of the 8259 interrupt controllers provides an eight-bit interrupt vector onto the EISA data bus SD&lt;7:0&gt;. The microprocessor then determines the starting address of the interrupt service routine based on the interrupt vector. The interrupt service routine is then executed. After the interrupt service routine has finished execution, the interrupted program state is restored from the stack, and program execution resumes at the appropriate instruction.
A mezzanine bus architecture standard known as the Peripheral Component Interconnect (PCI) is a relatively recent development. PCI was developed to allow for connection of highly integrated peripheral components on the same bus as the processor/memory system; that is, PCI standardizes a bus on which peripheral components can directly connect without the need for glue logic. Thus, PCI provides a bus standard on which high performance peripheral devices, such as graphics devices and hard disk drives, can be connected with the processor/memory module, thereby permitting these high performance devices to avoid the general access latency and the bandwidth constraints that would have occurred if the devices were connected to standard I/O expansion buses such as EISA. More details on the PCI bus can be obtained by review of the PCI Specification 2.0 from PCI Special Interest Group in care of Intel Corporation, which is hereby incorporated by reference.
In a computer system that comprises a PCI subsystem coupled to an EISA expansion bus, interrupt signals generated on the PCI bus must comply with the EISA system requirements. Thus, in PCI/EISA systems, interrupts generated on the PCI bus must be redirected or mapped to EISA interrupts. It is desirable that an interrupt generated by a peripheral device connected to the PCI bus be mapped to the same IRQ that it would have been allocated if the peripheral device was connected to the EISA bus. Furthermore, it is desirable that flexibility exists to allow a PCI interrupt to be redirected or mapped to any EISA interrupt.